In the design of a high-performance processor, improvement of performances of the processor implemented by just increasing a dominant frequency encounters bottlenecks. Currently, a mainstream trend is to design a processor with multiple cores. For example, a general processor for a Personal Computer (PC) is designed with dual cores, and a network processor is designed with tens of processor cores. In reality, tasks of the processor are always unbalanced in time domain, so that demands on the processing capability are also different. For example, when the network is busy, the full processing capability of the network processor may be required, but when the network is relatively idle, it is possible that the processing capability equivalent to only one or two processor cores is enough. The margin of the processing capability provides possible room for reducing power consumption of the processor. Considering the Low Power Design (LPD), some mature methods exist at the device level currently, such as, a method of stopping a clock signal of an idle device or a method of cutting off the voltage of the part.
In the prior art, when the processor is idle, the site is preserved, and then the whole processor enters the Sleep state. When a task is to be processed, the site is restored, and the processor is woken up to perform processing.
During the implementation of the present invention, the inventor finds that in the prior art, since the whole processor is in the Sleep state, no real-time data can be processed here. When a task is to be processed, the processor has to be woken up first, and then task information is sent, thus a task processing efficiency is affected.